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vLLM forks (RDNA2 / gfx1030)

WIP: Kernel behavior below is traced to fork source commits; published -extras Docker images may lag HEAD until rebuilt. See Verification status.

Fork landscape

#vllm-rdna (Sep 2026): the official gfx1030 vLLM source is the shared-org repo. File new PRs and issues there. Flash-Next work lives on rdna_extras. Published Docker Hub v0.31.0-extras landed 11 Oct 2026.

#Repo / branchRoleUse it when…
Officialopengfx1030/vllm-rdna @ rdna_extras (default)Hand-written RDNA HIP kernels + dispatch. Moved from the old personal blivioniag/vllm rdna2_extras line (repo 404 today). vLLM 0.31.0 as of 11 Oct 2026; old 0.28 line is rdna_extra/v0.28.0Clone, contribute, track HEAD
Flash-Next (older container)leapdragon/vllm-rdna2-qwen (e.g. rdna2/qwen38-flash-next)Older Flash-Next container + docs/rdna2. Day-to-day kernels / Hub bake live on org rdna_extras / v0.31.0-extras; this tree still receives occasional commits (last push 11 Oct 2026)Existing GHCR / compose that still points here; docs/rdna2 references
Historicalblivioniag/vllm @ rdna2_extras (public repo gone)Predecessor of the official repo. Do not file new PRs hereComparing old commit SHAs only; current Hub extras bakes clone the org repo

Day-to-day serving: pull blivioniag/vllm-rdna v0.31.0-extras (#announcements 11 Oct 2026). Source of truth for new kernel work is opengfx1030/vllm-rdna rdna_extras (now the v0.31.0 port). Older Hub tags stay for A/B. Do not assume org GHCR tags exist yet.

Companion (not an engine fork): leapdragon/vllm-rdna2-recipe (mirror opengfx1030/vllm-rdna2-recipe) collects compose/env recipes and open PRs (concurrent MTP, etc.). Wiki entry point: Recipes. #vllm-rdna (Sep 2026): the Flash-Next author treats the recipes repo as a parts pile (less active new work). Day-to-day Flash-Next optimization lives on org rdna_extras (Hub v0.31.0-extras); Concurrent-MTP PRs on the recipes repo are still worth cherry-picking into that stack.

Progress snapshot

For a dated Hub vs HEAD vs backlog table (MonoKernel, HIP defaults, PP3, INT4 KV, W4A8, open drafts), see Fork progress (26 Oct 2026). The chronicle below keeps per-PR detail.

Consolidation status (Sep 3–26 2026)

#vllm-rdna / public merges chronicle — expect this to move quickly:

TrackStatus
0.28 rebase on opengfx1030/vllm-rdnaHistorical (Sep 2026). Shipped as Hub v0.28.0-extras; day-to-day is now 0.31 (rdna_extras). Old line kept at rdna_extra/v0.28.0.
Flash-Next → org cherry-picks#vllm-rdna Sep 14–15: leapdragon Flash-Next work landed in rdna_extras. #announcements (11 Oct 2026): Hub v0.31.0-extras serves Flash-Next MTP-2. Prefer org HEAD / that Hub tag over older leapdragon GHCR. Earlier review-only PR #1 was the first rdna_ar pass.
Intel AutoRound / FP16 Flash-Nextopengfx1030/vllm-rdna#5 — closed (still draft, not merged, 14 Sep 2026). Validated short-run on 4× V620 (see overview). Not a Hub image; do not treat as open backlog.
QSA live-context prefillMerged opengfx1030/vllm-rdna#15 (20 Sep 2026) into rdna_extras. Bounds AMD QSA prefill scoring to the live prompt (decode / missing metadata stay capacity-wide). Folds superseded PR #12 V620 startup fixes. Combined-stack benches: overview. INT8 shadows and fused MTP-3 draft decode are not in the merge. Present in Hub v0.31.0-extras (11 Oct bake). #vllm-rdna (Sep 21–22): the #15 ~2k PP table did not reproduce on other 4× public-merge hosts (~1.1–1.45k). The unpublished recovery landed as #17 (next row).
Recipe ports + Hybrid W4A16 gfx10Draft opengfx1030/vllm-rdna#6 — in-tree Apache ports from the recipe book (Triton LDS/softmax, skinny MoE GEMV, MTP SupportsPP). RDNA2 HIP stays the auto default; Hybrid is opt-in (--linear-backend rdna_hybrid). Needs gfx1030 A/B.
Kernel gap audit after RDNA_ATTN portCommunity audit list (fix only): missing/partial layernorm bindings, FA int8/fp8 variants, some W8A8 / MLA / int8 cache bindings, VLLM_FORCE_CUSTOM_ALL_REDUCE wiring, MXFP4 oracle backend, stricter custom-paged-attention gate. Already clean on that pass: W4A16 dense+MoE, MLA sparse file, dynamo _SimpleCData fix, EXL3, arch helpers
V620 fast stack (#17)Merged opengfx1030/vllm-rdna#17 (23 Sep 2026) into rdna_extras. Ports the measured 4× TP4 serving stack: resident W4A16 MoE (pack INT4 into the RDNA2 layout once at load; skip per-chunk repack), Mamba state retirement across null gaps (backport vllm#55450 — previously a long-prompt preemption loop that halved usable context), and FULL_DECODE_ONLY graphs. PR-head 16k: ~1958 / ~1983 tok/s PP. #vllm-rdna (Sep 23): a second 4× host confirmed those 16k cells after regenerating TunableOp for its rocBLAS. Present in Hub v0.31.0-extras. Details: overview, TunableOp.
Flash-Next production4× V620 still the vLLM path; prefer latest rdna_extras (includes #17, #20, and the keep-FULL decode fix) over a stale leapdragon checkout. Published containers may lag. 3× PP3: current HEAD ships flashnext-pp3 / flashnext-pp3-mtp2 (#96, 13 Oct) — PP3 recipes. Sep 15–16 rdna_extras pins still garbage — troubleshooting. Community Sep 17–18 overlay alanoo81/flashnext-v620-pp3 is a snapshot — recipe; #general (Sep 23): overlay unmaintained. Graphs on HEAD: FULL_AND_PIECEWISE — uniform decode replays the FULL CUDA graph (same path as #17 FULL_DECODE_ONLY); mixed/prefill use piecewise. #20 (merged 24 Sep) made piecewise capture work but still redirected FULL→piecewise (~26–34 t/s decode). Follow-up commit 6c26c78d (#21 work; #vllm-rdna Sep 24 “fixed full and piecewise”) sets rocm_full_executes_as_piecewise → False. In-tree: docs/rdna2/V620-FULL-AND-PIECEWISE.md.
vllm-rdna-qaBlivionIaG/vllm-rdna-qa (#vllm-rdna Sep 17): maintainer QA / landing playbook for opengfx1030/vllm-rdna. Not a second kernel wiki.
Docker bakeSource moved to opengfx1030/vllm-rdna-docker. #announcements (11 Oct 2026): Hub blivioniag/vllm-rdna:v0.31.0-extras (same digest as v0.31.0-extras-rocm7.14.0; ROCm 7.14, torch 2.12, Triton 3.7.1) is the current extras bake and served Flash-Next MTP-2. Older v0.27.1-extras* / v0.28.0-extras* stay on Hub for A/B. Plain v0.27.1-rocm7.14.0 (non-extras) was called removable; keep rocm-rdna:7.14.0 as a packaging base. Kernels newer than the bake still want clone + host venv + tools/rdna/serve_rdna.sh.
0.28 MTP / 0.29 rebase#vllm-rdna Sep 18: no MTP support on the 0.28.0 extras line — rebase continues on rdna_extra/v0.29.0 to pick up upstream Qwen4Exp. Flash-Next long-prompt hosts that needed VLLM_USE_V2_MODEL_RUNNER=0 should re-A/B before bumping (V2 becomes the default on 0.29).
Upstream vLLM 0.30 / Qwen4 rebase#general (Sep 22): v0.30 released; official images cite ROCm 10.0. gfx1030 is still not in mainline. Side branch rdna_extra/v0.30.0 exists. Superseded as the day-to-day rebase by v0.31.0 (next rows).
GLM-5.3-Flash / Glm5Next (#2)Open #2 on side branch later/glm53-flash-awq — runtime-unverified (no GPU at author time); HIP gates default off. #vllm-rdna (Sep 30): a local 0.30 fork (not this PR) served wtdcode/GLM-5.3-Flash-AWQ-W4A16 on 8× TP=8 — recipes.
MTP unquantized drafter (#19)Merged opengfx1030/vllm-rdna#19 (24 Sep): detect MTP tensors that exporters left unquantized (missing quantization_config.dynamic exclusions) so the drafter loads instead of AttributeError on w2_weight. Hub -extras lags.
MTP draft unbreak (700753d9)rdna_extras HEAD (25 Sep): swallow failing amdsmi_shut_down() so MoE config lookup can fall back; Qwen4Exp MTP local-argmax draft sampling. Author-host MTP-2 boots but stays ~0.73–0.85× vs MTP-0. #vllm-rdna Sep 25 confirmed “closer, still a loss”. MTP=2 path is in Hub v0.31.0-extras — acceptance still Needs verify. Quantization.
GPTQ BLOCK_KN_SIZE (#18)Open #18: bump GPTQ BLOCK_KN_SIZE 128 → 256 on gfx1030. #vllm-rdna (Sep 24): hold merge until an M > 32 sweep through at least 2048.
MTP under pipeline parallelUpstream vllm#46994 merged (#vllm-rdna Sep 15). Needed for PP3 + MTP on 3× V620. In-tree recipes #96 (13 Oct): flashnext-pp3 / flashnext-pp3-mtp2 — PP3. Hub v0.31.0-extras (11 Oct bake) still lags.
rdna_ar / custom all-reduce (#22)Merged #22 (27 Sep): two-shot rdna_ar so serve scripts can leave VLLM_FORCE_CUSTOM_ALL_REDUCE=0. Library default for VLLM_RDNA_AR stays off (failed self-test falls back to RCCL). #vllm-rdna Sep 15–24: force-custom crashed one host. A/B on your topology before making it a default.
Disagg prefill/decode (#23)Open #23: local PCIe P2P KV bridge so prefill and decode can sit on different PLX switches (TP stays inside a switch; KV handoff is SDMA). #vllm-rdna (Sep 24): stated as a multi-system objective. Needs verify — not a recipe yet.
hippihxBlivionIaG/hippihx (#hippihx Sep 16): HIP kernel op zoo meant to keep rdna_extras thin. Not wired into a published image yet.
Prefix cache on Flash-Next#vllm-rdna Sep 17: pre-fix rdna_extras reported 0% hits. Fix: e45dd5cb (QSA ring / hybrid min). Port of vllm#55506 is 741e5bc3 (V2 mamba spec-decode tables) — did not replace the 0% fix. — troubleshooting.
DeepSeek-V4 FlashCommunity INT4 + gfx1030 tree (yiminyuan, #vllm-rdna Sep 17) — recipes. In-tree launcher recipe RECIPE=dsv4-flash under tools/rdna/recipes/ (fp8 dense + MXFP4 experts, breakable graphs on). Needs verify.
LMCacheStill no published gfx1030 recipe. Do not remake the standalone image — run official lmcache/standalone in CPU mode and add a vLLM connector (LMCacheConnectorV1 / LMCacheMPConnector) to a bare-metal / venv rdna_extras serve. Official CUDA image lmcache/vllm-openai is not the RDNA path. #lmcache (Sep 23–24): a community 0.5.6.dev wheel built against gfx1030; official kernels are CDNA-only (generic fallback + Mamba align issues). Hybrid Qwen (MambaSpec + QSA FullAttentionSpec) needs HMA; LMCacheConnectorV1 is not HMA-capable and dies at startup (Failed to promote local KV cache specs). — troubleshooting.
Upstream CPU KV offload (ROCm)#vllm-rdna Sep 20: vllm#57160 (mainline, not 0.29) uses private pinned tensors for CPU KV offload after cudaHostRegister failures on large TP. Tracking note only — the gfx1030-facing fix is the next row.
RAM KV offload (#24)Merged opengfx1030/vllm-rdna#24 (27 Sep 2026) into rdna_extras. Fixes ROCm RAM-tier corruption (per-rank pinned buffers, hybrid group indices, MTP/EAGLE trailing block, scratch-group filter). #vllm-rdna Sep 26–27: ~190k RAM→VRAM in ~0.4 s; three ~150k sessions while VRAM held ~270k. PR swap: ~2.1 s reload of ~200k, decode ~112 t/s (no 1 t/s collapse). SSD tier untested. In Hub v0.31.0-extras. — troubleshooting.
Skinny HIP MoE 9–16 rows (#26)Merged #26 (27 Sep). Opt-in VLLM_ROCM_MOE_SKINNY_MAX_M=16 so concurrent MTP-2 batches (9–16 token rows) stay on native HIP instead of tile Triton. Default cap remains 8. PR regular-text c=3: +11% aggregate gen. No single-chat claim; coding-suite dominant_repeated_token failures retained.
MTP draft graph (30632b2)rdna_extras (27 Sep): capture the speculator draft graph at max_num_reqs so MTP-2 c=8 is not eager. Author-host +18% (8×1k) / +5% (8×16k). Still ~0.87× vs MTP-0 at 16k. #vllm-rdna: better, not great.
FA-RDNA2 kernel pass (#28)Merged #28 (28 Sep). Causal tile skip / in-place FA output / GQA softmax. Not GPU-validated on gfx1030 at merge (offline / CPU emulation only). Draft #29 (split decode for MTP verify) is stacked on it and also untested on device. Do not claim tok/s from either.
Adaptive prefill (#36)Merged #36 (5 Oct 2026). Opt-in VLLM_RDNA_DYNAMIC_PREFILL=1 self-tunes --long-prefill-token-threshold and --prefill-schedule-interval for mixed prefill+decode. Default off. #vllm-rdna (Oct 4–5): static flags still paused decode during prefill; the dynamic path kept decode moving (~25 t/s burst at 3 decode + 1 prefill). Author Oct 5: recovered about half the mixed-prefill cliff (below 500 → ~1100 PP) and auto-adjusts with load. Synthetic benches called a poor measure. In Hub v0.31.0-extras (opt-in). — troubleshooting.
MoE expert DRAM cache (#37)Draft #37: earlier opt-in hot-expert VRAM / host-RAM cache. Superseded by merged #146 (28 Oct) — 2× serve. Do not treat #37 as a recipe.
INT4 PLE (#49) + disk sidecarMerged #49 (11 Oct 2026) into rdna_extras, then shipped in the v0.31.0 release. Launcher PLE=bf16|int4|int4-disk + PLE_QUANT_DIR=…/ples_int4 (primitive-ai/Qwen3.8-Flash-Next-PLE-quant). #announcements (11 Oct): all three modes tested on 4× V620; speed at parity. #vllm-rdna (Oct 11): INT4 host-RAM working set is ~35 GB, not the earlier inflated ~90 GB figure. Docker: -v …/ples_int4:/ples_int4 -e VLLM_PLE_QUANT_DIR=/ples_int4 (-e VLLM_PLE_CPU_OFFLOAD=1 for disk).
v0.31.0 release (#47)#47 closed; #announcements (11 Oct 2026): rdna_extras = upstream vLLM v0.31.0 + RDNA port. Old 0.28 line: rdna_extra/v0.28.0. Hub blivioniag/vllm-rdna:v0.31.0-extras. One launcher: bash tools/rdna/serve_rdna.sh RECIPE=… (flashnext-mtp2, flashnext-mtp0, flashnext, 27b-awq, 27b-exl3, dsv4-flash, full). Author-host 4× V620 TP=4 (probes, PPL, prefix cache, concurrency, 0 GPU faults): Flash-Next AWQ ~2000 tok/s prefill, 45 (MTP-0) / 69 (MTP-2) tok/s decode, ~205 tok/s aggregate at 8 users — Fork-source. Also tested 27B AWQ (+W4A8, +TP=2), Qwen3.6-35B-A3B GPTQ MTP-0/2, DeepSeek-V4-Flash MXFP4. #vllm-rdna (Oct 11): P2P=0 for hosts without PCIe P2P. PP3 recipes are HEAD-only (next rows) — not in the 11 Oct Hub bake.
PP3 Flash-Next (#96 / #95)Merged #96 (13 Oct): RECIPE=flashnext-pp3 / flashnext-pp3-mtp2. Under PP the MTP drafter no longer keeps a second GPU embedding/lm_head; it shares the target’s on that stage. #95: int8 dense shadows in row chunks (load used to OOM a ~2.4 GiB fp32 temporary). #general (13 Oct) author-host 16k/1k: MTP-0 1848/38 c=1, 771/7.7 c=8; MTP-2 1866/70.9 c=1, 1071/10.1 c=4 — Community. PP3.
Prefix-cache off (#97)Merged #97 (14 Oct): ENABLE_PREFIX_CACHING=0 now passes --no-enable-prefix-caching. Omitting the enable flag left vLLM’s default on.
Asymmetric W4A16 MoE (#98)Merged #98 (14 Oct): RDNA2 W4A16 MoE no longer synthesizes symmetric zero points. Asymmetric compressed-tensors checkpoints (e.g. cyankiwi/*-AWQ-INT4, group 32, int8 zeros) used to fall back to generic Triton WNA16 MoE. Asymmetric 8-bit checkpoints still fall back. — quantization.
Flash-Next TP4 HW queues (#107)Merged #107 (16 Oct): GPU_MAX_HW_QUEUES=4 on Flash-Next TP4 recipes. Launcher default stays 2. Neutral with fork kernels off; removes per-rank skew when rdna_mono_* kernels are in the graph.
rocprofiler register (#108)Merged #108 (16 Oct): launchers default ROCPROFILER_REGISTER_ENABLED=0. #vllm-rdna (16 Oct): rocprofiler registration spun ≥1 core per GPU and kept the host out of idle. Distinct from ROCR busy-spin. Profiling: set =1.
Flash-Next MonoKernel (#94)Merged #94 (16 Oct) into rdna_extras. Opt-in persistent decode kernel for Qwen3.8-Flash-Next (qwen4_exp) on gfx1030 TP4: --monokernel or VLLM_ROCM_MONO_DECODE=1 (off by default; backport of vllm#61082). Prefill, mixed batches, the MTP drafter, and TP all-reduce stay on the current path. Not in Hub v0.31.0-extras. Recipes do not turn it on yet. Serve: MonoKernel. Follow-up docs PR #120 (open).
Triton 3.9 drops gfx1030#vllm-rdna (17 Oct): RDNA1/RDNA2 are removed from Triton 3.9+. Hub extras and the host venv pin 3.7.1 (ROCm 7.14) / 3.5.1 (ROCm 7.2). Do not bump Triton “to latest” on a gfx1030 venv. The fork’s HIP path is the long-term escape; stay on the pinned wheel until then.
MonoKernel QSA HIP (#126)Merged #126 (18 Oct). Under --monokernel, QSA indexer store / one-launch epilogue / scoring move to HIP. Default path unchanged. Opt-in VLLM_RDNA_QSA_HIP=1 without --monokernel also uses the HIP indexer. Not Hub.
Dynamic MTP opt-in (#127)Merged #127 (18 Oct): #119 dynamic MTP graph shapes, opt-in. Fixed MTP-2 is unchanged unless num_speculative_tokens_per_batch_size is set. #vllm-rdna (22 Oct): leave the schedule off — community A/B blamed it for token-repeat loops. Proper dynamic drafting is still open #125.
rdna_ar sticky abort (#128)Merged #128 (19 Oct). Rare silent decode hang: GPUs at 99% util / 0% memory, host idle, RPC call … timed out, no WEDGED. After one lost peer flag the one-shot re-waited 120 s per collective. Now fails fast as WEDGED and the next boot falls back to RCCL. — hang.
HIP set default-on (#130, closes #99)Merged #130 (19 Oct). Ports #99 QSA/GDN/HC HIP kernels with MonoKernel #126. Flash-Next recipes now default VLLM_RDNA_ALL_HIP, VLLM_RDNA_QSA_HIP, VLLM_RDNA_HC_PREFILL_HIP, and VLLM_GDN_HIP_PREFILL=1 (EXL3 unchanged). Set those to 0 to get Triton back. Author-host ITL −6 to −8% without --monokernel. Hub v0.31.0-extras lags. Vectorized one-shot (#129) stayed out.
Non-mono graph hang (#131)Merged #131 (19 Oct). Intermittent hang without --monokernel: workers silent, ~300 s RPC timeout. gfx10x SharedExperts no longer forks to an aux HIP stream inside CUDA-graph capture (ROCm 7.14 signal-reuse). Eager overlap stays. — hang.
Flash-Next DFlash2 (#132)Merged #132 (21 Oct): RECIPE=flashnext-dflash2 — wtdcode AWQ target + incoai/Qwen3.8-Flash-Next-DFlash2 BF16 drafter, FA-RDNA2 BLHNC draft attention. Default 3 draft tokens; DFLASH_TOKENS=2 is the measured 16k c=8 ladder. Paired A/B: native MTP-2 still faster in all four cells. #vllm-rdna (22 Oct): maintainer same for agentic; DFlash2 can win short / single-user. Not Hub. — DFlash2.
EXL3 Flash-Next (#117)Merged #117 (17 Oct): RECIPE=flashnext-exl3 for turboderp/Qwen3.8-Flash-Next-exl3 (3.05bpw). PLE=exl3 mmaps ngram_embedding.safetensors via the CPU sidecar; MTP=0; expert-parallel on (EXL3 128-wide blocks do not split under TP=4 alone). Drafts #122/#123/#124 cover MTP / vision / MoE cut. Not Hub. — Serve scripts.
MTP-2 MonoKernel (#137)Merged #137 (24 Oct): MTP Mono K1/K2 sticky-fault containment + opt-in post-proposal TP status reduce before tokens return. Ordinary native MTP-2 skips that collective. Graph / eager fault qualification noted in the PR. Still opt-in via --monokernel. Not Hub.
INT4 KV int4_fp16_block (#138)Merged #138 (25 Oct): packed INT4 + FP16 per-32-channel block scales as a real CacheDType. Native write/read on the non-MonoKernel QSA path; other backends refuse the dtype (silent corruption risk). Opt-in --kv-cache-dtype int4_fp16_block. Default FP16 KV unchanged. #vllm-rdna (21 Oct): maintainer still prioritizes restoring INT8 KV (draft #71) for day-to-day. Not Hub.
fp16 SSM + W4A8 default (#140)Merged #140 (26 Oct): GDN prefill can keep mamba state in fp16 (page ~half → denser KV); launcher derives prefill budget from the mamba block; 27b-awq recipe defaults W4A8=1 (int8-activation prefill GEMMs for M≥33; decode stays W4A16). Author-host 4× TP4 27B: 16k c=1 PP 860 → 1075 tok/s; c=8 agg out 42.5 → 52.3; paired PPL ~4.94 → 4.91. Not Hub.
TP2 AWQ MoE expert offload (#146)Merged #146 (28 Oct): Flash-Next TP=2 / EP=2 expert-weight spill to pinned host RAM with a bounded GPU slot cache (default 96 slots/layer, lfu_lru or lru). #vllm-rdna (28 Oct): V1 landed. In-tree launcher is tools/rdna/mono/serve_offload.sh — not a serve_rdna.sh RECIPE= yet. Design notes: docs/rdna2/moe-offloading-target.md. Author-host 2× V620, wtdcode AWQ-W4A16, MTP-2, 16 GiB native CPU KV: 16k/1024 c=1 ~19.8 tok/s aggregate (TTFT ~17 s, ~30 decode); c=8 ~26.7 agg; 32k/256 c=1 ~30 decode / TTFT ~34 s — Fork-source, no controlled resident-vs-offload speedup claimed. Offload launcher defaults VLLM_RDNA2_W4A16_DETERMINISTIC_DENSE=1 (resident recipes stay as they were). Not Hub. — 2× serve.

Official-fork feature set called out in-channel (HIP): MXFP4, AWQ INT4, GPTQ INT4, GDN prefill/decode linear attention, FA-RDNA2, one-shot all-reduce, FULL_AND_PIECEWISE, EXL3, MTP=2. Treat Hub v0.31.0-extras as the current extras bake; clone HEAD for work after that tag. Readable snapshot: Fork progress.


The rdna_extras fork

The official extras source is opengfx1030/vllm-rdna on the default rdna_extras branch (formerly personal blivioniag/vllm rdna2_extras — public repo 404 today). It adds hand-written RDNA2 HIP kernels and the vLLM plumbing to dispatch to them.

Current Hub extras bakes (v0.28.0-extras, v0.31.0-extras) clone this org branch via vllm-rdna-docker (VLLM_REPOSITORY=…/opengfx1030/vllm-rdna.git, VLLM_REF=rdna_extras). Older v0.26 / v0.27.1-extras* bake targets still name the removed personal BlivionIaG/vllm @ rdna2_extras clone. Pull Hub v0.31.0-extras for serving; clone the org repo to contribute.

Why it exists: RDNA2 (gfx1030) has no matrix/WMMA cores — those arrived with RDNA3 (gfx11xx). So quantized GEMM, attention, and MoE have to be implemented efficiently on RDNA2’s regular vector ALUs. This fork does exactly that (with RDNA3 WMMA variants where it makes sense).

INT4/W4A16 on gfx1030 does not use native int4 compute. The RDNA2 kernels dequant on the fly using vdot2 fp16 instructions with int4 packed via dp4a. Community testing found no faster INT8-based HIP kernel vs fp16 for these paths — fp16 dequant is the winning approach on V620.

Branches

BranchPurpose
mainFork baseline tracking upstream vLLM.
rdna_extrasDefault. Aggregated RDNA extras (HIP kernels, EXL3 WIP, …). File PRs here.

Historical names on the old personal fork (feat/enable-gfx1030, perf/rdna2_w4a16, rdna2_extras) are superseded. Only the older v0.26 / v0.27.1-extras* bake targets still name that removed repo; current extras bakes use VLLM_REF=rdna_extras on opengfx1030/vllm-rdna.

What’s in it

The custom device code lives under csrc/rocm/*_rdna2.cu (with _rdna3 variants where WMMA applies), wired into vLLM through Python kernel/layer modules and covered by targeted tests under tests/kernels/.

Attention

  • fa_rdna2.cu — a FlashAttention kernel tuned for RDNA2, exposed via vllm/v1/attention/ops/fa_rdna2_backend.py and the vllm/v1/attention/backends/rdna_attn.py backend. Now supports head_size=256 on gfx10x (needed for Qwen3.8-27B-AWQ-INT4; previously capped at 128 and caused Triton GDN compile hangs). #vllm-rdna (Sep 22–24): when the extras fork went public the maintainer dropped the FP16 FA pieces to focus on validating W4A16. In-tree fa_rdna2 is still the org target, but it is currently disabled / not working after the #17 stack changes (prefix-cache + piecewise first). Independent 2kiss/flash-attention-rdna2 is stale — do not treat it as a drop-in. Needs verify.
  • sparse_mla_rdna2.cu + rocm_rdna2_mla_sparse.py — sparse MLA (multi-head latent attention, DeepSeek-style).
  • indexer_paged_mqa_rdna2.cu — paged MQA indexer.

Quantized GEMM (mixed-precision linear)

  • q_gemm_rdna2.cu / q_gemm_rdna2_prefill.cu (+ q_gemm_rdna2_common.cuh) — W4A16 quantized GEMM for decode and prefill.
  • q_gemm_w8a16_fp8_rdna2.cu, gemm_w8a8_fp8_dense_rdna2.cu — FP8 W8A16 / W8A8 paths.
  • qdq_4_rdna2.cuh, qdq_8_rdna2.cuh, qdq_fp8_rdna2.cuh — quant/dequant helpers.
  • Python: model_executor/kernels/linear/mixed_precision/rdna2_w4a16.py, .../scaled_mm/rdna2_w8a16_fp8*.py, rdna2_w8a8_fp8.py, and the rdna_hybrid_w4a16.py selector.
  • EXL3 (in-tree on rdna_extras; #announcements 11 Oct 2026 lists it on the v0.31.0 extras bake / RECIPE=27b-exl3): exl3_hadamard.cu, exl3_dot2_*.cu, plus vllm/.../quantization/exl3.py. Still experimental. #vllm-rdna (Sep 24): rdna_extra/v0.29.0 added mul1 so existing EXL3 packs can load. #vllm-rdna (Sep 29–30) + rdna_extras commits (30 Sep–1 Oct): mul1 / K=1..8 plus the v0.30 loader rewrite are on HEAD and GPU-run on gfx1030 (215/215 tests; 27B 3.00 bpw mul1 TP=4 graphs). #vllm-rdna (Oct 2): that path is mul1-tested only — 3inst packs are untested. Draft #32 was the earlier kernel-port PR. Older Hub v0.27.1-extras* tags do not have this — Quantization.

MoE (mixture of experts)

  • moe_q_gemm_rdna2.cu, moe_w8a16_rdna2.cu, moe_w8a16_fp8_rdna2.cu — quantized expert GEMMs.
  • Python experts fused_moe/experts/rdna2_mxfp4_moe.py, rdna2_w8a16_fp8_moe.py, and compressed_tensors MoE glue (..._fp8_rdna2, ..._w4a4_mxfp4_rdna2, ..._wna16_rdna2).

#vllm-rdna (Sep 19): a quality A/B reported the fused HIP MoE kernel is not deterministic. On the same server and the same tokens, about 3.5% of the most-probable tokens changed between runs, costing about +0.2–0.3% perplexity versus the best reference that host could run. The Triton MoE path was bit-identical across repeats. Cause not isolated (fp16 accumulation order vs a real race). Proposed, not landed as of Sep 19: replace the atomic_add_pk4_f16 CAS loop with global_atomic_add_f32 (fewer atomics, possibly worse bandwidth). #vllm-rdna (Sep 30): an fp32 deterministic MoE mode was described as opt-in because it cuts throughput — flag name was not posted; do not invent an env var. Default stays the faster path. Needs verify — do not switch kernels on this note alone.

GDN (gated delta-net / linear attention)

Kernels for gated-delta-net models (e.g. Qwen3.8-27B hybrid linear attention). As of Aug 2026 the full GDN chain is hand-ported to HIP — no Triton JIT on the hot path:

KernelFileRole
Decodegdn_decode_rdna2.cuPacked decode; fork microbench reports ~9.3× vs Triton at B=1 (community)
Prefill prepgdn_prefill_prep_rdna2.cuQ/K/V staging
Prefill KKTgdn_prefill_kkt_rdna2.cuKKT accumulation
Prefill solve WYgdn_prefill_solve_wy_rdna2.cuWY solve
Prefill delta_hgdn_prefill_delta_h_rdna2.cuDelta-h update
Prefill outputgdn_prefill_o_rdna2.cuOutput projection

This replaces the Triton FLA GDN path that previously caused 16k/1k prefill hangs and slow decode on hybrid models. Recent tuning commits improved delta_h register pressure, o-kernel block-vector width, and prep-kernel vectorization.

Using it

The easiest path is a prebuilt -extras image — no compilation required:

docker run -it --rm \
  --device /dev/kfd --device /dev/dri --group-add video --group-add render \
  --security-opt seccomp=unconfined --ipc host -p 8000:8000 \
  docker.io/blivioniag/vllm-rdna:v0.31.0-extras \
  vllm serve <model> --dtype float16

See Running (Docker) for the full run recipe and Building images for how the -extras variant is produced (VLLM_VARIANT=extras-fork, current extras targets VLLM_REF=rdna_extras on opengfx1030/vllm-rdna).

Kernel dispatch on gfx1030

On -extras images, vLLM picks kernels based on quantization format:

Quant methodKernel selectedHow to force
GPTQ (AutoGPTQLinearMethod)RDNA2W4A16LinearKernelVLLM_DISABLED_KERNELS=ExllamaLinearKernel,TritonW4A16LinearKernel
AWQ (dense, gfx10x)RDNA2W4A16LinearKernelSame VLLM_DISABLED_KERNELS as GPTQ; AWQ dense now routes through the native W4A16 kernel
FP8 W8A16 / W8A8gemm_w8a16_fp8_rdna2 etc.Automatic on -extras when model uses FP8

Check startup logs for lines like Using RDNA2W4A16LinearKernel for AutoGPTQLinearMethod. If you see TritonW4A16LinearKernel or ExllamaLinearKernel instead, the RDNA2 quant path isn’t active.

Attention backends

  • VLLM_USE_RDNA2_FA=1 — enables the custom fa_rdna2.cu FlashAttention backend on Hub -extras. #vllm-rdna (Sep 15): on current Flash-Next / rdna_extras HEAD, native FA is still WIP — community A/B used VLLM_USE_RDNA2_FA=0 (and sometimes VLLM_GDN_HIP_PREFILL=0) when chasing PP3 correctness. Do not copy that disable onto a working 0.27.1 -extras 27B serve.
  • --attention-backend RDNA_ATTN — alternative RDNA-tuned attention path (useful for Qwen models with head size 256 where generic AMD Triton FA is slow or broken).
  • FLASH_ATTENTION_TRITON_AMD_ENABLE=TRUE — enables AMD Triton FA as a fallback; often slower on gfx1030.
  • Optional FA-RDNA2 knobs on rdna_extras (rdna_attn.py, Oct 2026): VLLM_FA_RDNA2_GQA_MODE (default subgroup), VLLM_FA_RDNA2_SPLIT_DECODE (default 1). A/B only — not a serve recipe.

#vllm-rdna (13 Oct): FA-RDNA2 is general attention, not “dense models only”. On Flash-Next, full-attention layers are owned by the QSA path (Qwen4ExpQSA*), which picks its Triton backend directly and does not consult --attention-backend / VLLM_USE_RDNA2_FA. Seeing Triton in the stack for those layers is expected. A full switch would need HIP QSA split-K attention plus INT4 PLE n-gram lookup — still open work (community cited fork backlog around #64). Prefer not treating FA flags as a Flash-Next speed lever until that lands — troubleshooting.

On v0.27.1, hybrid GDN models may still auto-select ROCM_ATTN even with VLLM_USE_RDNA2_FA=1 for the attention layers — that’s expected. The GDN linear-attention layers now use the native HIP kernels above (not Triton FLA). For graph capture issues, see CUDA graphs and vLLM troubleshooting.

CUDA graph capture (TP comm fix)

A common _SimpleCData.__new__ crash during V2 cudagraph capture on multi-GPU TP setups was fixed by marking TP communication wrappers with allow_in_graph. With current -extras images, CUDA graphs are the preferred fast path — you should not need --enforce-eager for this class of failure anymore. On multi-GPU, if AOT compile cache replay misbehaves, try VLLM_USE_AOT_COMPILE=0 VLLM_DISABLE_COMPILE_CACHE=1.

Disabling fallback kernels

export VLLM_DISABLED_KERNELS=ExllamaLinearKernel,TritonW4A16LinearKernel

This is the main lever for forcing GPTQ onto the native RDNA2 W4A16 path. The variable accepts a comma-separated list of kernel class names registered in vLLM’s linear-kernel registry.

To test Exllama instead (still relevant on some quants per #general):

--linear-backend exllama

Omit VLLM_DISABLED_KERNELS when testing Exllama — it competes with the RDNA2 kernel for dispatch.

Building from source (advanced)

Create the venv and install torch first — the ROCm 7.2.0 and 7.14.0 commands are on Host venv. Dockerfile.vllm then does an editable install (not requirements/dev.txt):

git clone -b rdna_extras https://github.com/opengfx1030/vllm-rdna.git
cd vllm-rdna
export PYTORCH_ROCM_ARCH=gfx1030
export ROCM_HOME="${ROCM_HOME:-/opt/rocm}"
VLLM_USE_PRECOMPILED=0 ENABLE_CK=0 FLASH_ATTENTION_TRITON_AMD_ENABLE=TRUE \
  uv pip install -e . --no-build-isolation

On ROCm 7.2.0 only, add --torch-backend=rocm7.2. On 7.14.0, leave it off and install the multi-arch device wheels first. Details: Host venv.

The kernels have their own tests, e.g.:

pytest tests/kernels/quantization/test_rdna2_w4a16.py
pytest tests/kernels/attention/test_fa_rdna2_shape_sweep.py

These kernels are actively evolving. Treat the fork as experimental, pin to a known-good image tag for reproducible serving, and file issues on opengfx1030/vllm-rdna if you hit correctness or performance problems.